1. Field of the Invention
The present invention relates to a voltage level shifter and, more particularly, to a voltage level shifter capable of operating at high speed without distortion of the waveform of an output voltage even when an input voltage is very low.
2. Description of the Related Art
Modern integrated circuit systems generally employ two different levels of power supply voltages for core logic units and input/output units of the integrated circuit systems, respectively. Take the 0.13 xcexcm process as an example, the core logic unit is typically applied with a power supply voltage with a level of 1.2 volts while the input/output unit is typically applied with a power supply voltage with a level of 3.3 volts. Due to a difference between operation voltages, there are typically two kinds of transistors that are different in a thickness of a gate oxide layer from each other, i.e. thin oxide transistors and thick oxide transistors, used in the integrated circuit system. In general, the thin oxide transistor is utilized within the core logic unit while thick oxide transistor is utilized within the input/output unit. Consequently, it is necessary for the integrated circuit system to use a voltage level shifter as an interface device between the core logic unit and the input/output unit, thereby performing a function of mapping a voltage range applicable to operations of the core logic unit into a voltage range applicable to operations of the input/output unit.
FIG. 1(a) is a circuit configuration diagram showing a conventional voltage level shifter 1. Referring to FIG. 1(a), the conventional voltage level shifter 1 includes a first and second P-type MOS transistors PG1 and PG2, a first and second N-type MOS transistors NG1 and NG2, and an inverter INV. Each of the first and second P-type MOS transistors PG1 and PG2 and each of the first and second N-type MOS transistors NG1 and NG2 are both a thick oxide MOS transistor having a gate oxide layer with a thickness of about 65 angstroms.
A gate electrode of the first P-type MOS transistor PG1 is electrically connected to an output terminal O of the voltage level shifter 1 and a source electrode thereof is electrically connected to a first voltage level VccH. A gate electrode of the second P-type transistor PG2 is electrically connected to a drain electrode of the first P-type MOS transistor PG1, a drain electrode thereof is electrically connected to the output terminal 0 of the voltage level shifter 1, and a source electrode thereof is electrically connected to the first voltage level VccH. For example, the first voltage level VccH is 3.3 volts. A gate of the first N-type MOS transistor NG1 is used as an input terminal I of the voltage level shifter 1, a source electrode thereof is grounded, and a drain electrode thereof is electrically connected to the drain electrode of the first P-type MOS transistor PG1. A source electrode of the second N-type MOS transistor NG2 is grounded and a drain electrode thereof is electrically connected to the drain electrode of the second P-type MOS transistor PG2. An input node of the inverter INV is electrically connected to the input terminal I of the voltage level shifter 1 and an output terminal thereof is electrically connected to a gate electrode of the second N-type MOS transistor NG2.
FIG. 1(b) is a circuit configuration diagram showing another conventional voltage level shifter 2. Although the voltage level shifters 1 and 2 shown in FIGS. 1(a) and 1(b) are different in the circuit configuration from each other, their relationships of input voltages versus output voltages are substantially the same. In the following, the relationship between the input voltage and the output voltage of the conventional voltage level shifter will be described in detail with reference to FIG. 2.
FIG. 2 is a timing chart showing numerical simulations of waveforms of an input voltage and an output voltage of the conventional voltage level shifter 1 or 2 shown in FIG. 1(a) or 1(b). Referring to FIG. 2, when a rectangular wave with a voltage range from 0 to 1.0 volt is used as an input voltage, the conventional voltage level shifter 1 or 2 raises the maximum level of an output voltage up to about 3.3 volts, i.e. the first voltage level VccH. However, it is clearly found from FIG. 2 that the conventional voltage level shifter 1 or 2 has a problem that the waveform of the output voltage is seriously distorted and therefore no longer remains as a rectangular wave. This is because the input voltage as low as 1.0 volt cannot sufficiently turn on the first and second N-type MOS transistors NG1 and NG2 since each of them belongs to a thick oxide transistor with a threshold voltage of about 0.8 volts. Moreover, as shown in FIG. 2, a time delay Tr occurs between the rising edge of the output voltage and the rising edge of the input voltage while a time delay Tf occurs between the falling edge of the output voltage and the falling edge of the input voltage. These rising and falling time delays Tr and Tf result in impossibility of high-speed operations of the conventional voltage level shifter 1 or 2.
In view of the above-mentioned problems, an object of the present invention is to provide a voltage level shifter capable of preventing the output voltage from distortion even when the input voltage level is very low.
Another object of the present invention is to provide a voltage level shifter capable of operating at high speed even when the input voltage is very low.
According to one aspect of the present invention, a high speed voltage level shifter with a low input voltage includes a first and second thick oxide P-type MOS transistors, a first and second thick oxide N-type MOS transistors, a first and second thin oxide N-type MOS transistors, a third and fourth thin oxide N-type MOS transistors, and an inverter. Source electrodes of the first and second thick oxide P-type MOS transistors are electrically connected to a high voltage level. For example, the high voltage level is a power supply voltage applied to an input/output unit in an integrated circuit system and is about 3.3 volts. Gate electrodes of the first and second thick oxide N-type MOS transistors are electrically connected to a reference voltage level. For example, the reference voltage level is provided from a voltage divider. Gate electrodes of the first and second thin oxide N-type MOS transistors are electrically connected to a low voltage level. For example, the low voltage level is a power supply voltage applied to a core logic unit in the integrated circuit system and is about 1.2 volts.
The input voltage is coupled to a gate of the third thin oxide N-type MOS transistor and, through the inverter, to a gate of the fourth thin oxide N-type MOS transistor. When the input voltage is very low, the third and fourth thin oxide N-type MOS transistors are sufficiently turned on since their threshold voltage is relatively low.
It is necessary for the reference voltage level according to the present invention to be larger than a threshold voltage of the first thick oxide N-type MOS transistor and simultaneously to be equal to or smaller than a sum of twice of the low voltage level and the threshold voltage of the first thick oxide N-type MOS transistor, thereby protecting the third and fourth thin oxide N-type MOS transistors from damage caused by the high voltage level.
According to another aspect of the invention, a high speed voltage level shifter with a low input voltage is provided to be different from the above-mentioned high speed voltage level shifter in that the third thin oxide N-type MOS transistor is deleted and an output node of the inverter is electrically connected to, besides the gate electrode of the fourth thin oxide N-type MOS transistor, a drain electrode of the first thin oxide N-type MOS transistor.